Column redundancy allows a memory array to replace a bad column with a redundant column. This redundancy can be performed using sense-amplifier (SA) shifting or I/O shifting. A memory 100 with sense-amplifier shifting is shown in FIG. 1. Two independent memory arrays or banks are included in memory 100: a bank 1 array and a bank 0 array. Each memory bank has its own set of sense amplifiers 101 for sensing the bit lines for memory bank. Each sense amplifier 101 senses from four corresponding bit lines 102 from its corresponding memory bank. In other words, there is a 4:1 bit-line multiplexing with regard to each sense amplifier 101 for a given memory bank. An array of read lines 104 are shared by sense amplifiers 101 for memory bank 0 and memory bank 1. The bit lines 102, memory cells in bank 0 and bank 1 as well as the corresponding sense amplifiers 101 and read line 104 are denoted herein as a “column.” In other words, a column refers to the structure in any given memory bank to drive a sense amplifier's read line 104. That structure would of course include sense amplifier 101 and the associated bit lines 102 and memory cells coupled to those associated bit lines 102.
For illustration clarity, only a single initial column 135 and a subsequent column 135 are demarcated by dotted lines in memory 100. Each column 135 includes four corresponding bit lines 102 in memory bank 0 and memory bank 1. As known in the memory arts, each sense amplifier 101 is configured to respond to a sense enable signal (not illustrated). If the sense enable signal to a given sense amplifier 101 is asserted, that sense amplifier 101 will drive out a bit decision onto its read line 104.
Memory 100 responds to a read operation by outputting a retrieved word Dout from an output stage 120, Dout is a 32-bit wide retrieved word ranging from a first word bit Dout[1] to a last word bit Dout[32]. Each word Dout can either be an odd word or an even word depending upon whether it was sensed from odd or even columns. In other words, columns 135 are divided into even (E) and odd (O) columns. An even column includes an even sense amplifier for each memory bank. Similarly, an odd column includes an odd sense amplifier for each memory bank. A first even column and a first odd column correspond to Dout[1], depending upon whether the word is odd or even. Similarly, a second even column and a second odd column correspond to Dout[2], and so on such that a 32nd even column and a 32nd odd column correspond to Dout[32]. Given this odd or even value for each word bit, a first stage of 2:1 multiplexers 125 in output stage 120 enables an 8:1 bit line multiplexing with regard to each word bit.
Just like the odd and even column pairs, each multiplexer 125 corresponds to a bit position in the word Dout. For example, a first multiplexer 125 corresponds to Dout[1], a second multiplexer 125 corresponds to Dout[2], and so on. Each multiplexer 125 can select between the even and odd columns for its corresponding word bit with regard to its S1 and S2 inputs. For example, an initial multiplexer 125 receives the read line 104 for the first even column 135 at its S2 input and receives the read line 104 for the first odd column at its S1 input. Each multiplexer 125 may thus be considered to receive an odd input and an even input.
The sense enable signal to sense amplifiers 101 differentiates between even and odd columns and also between banks. The sense enable signal for a given memory bank may thus have a even state that triggers the sensing of the even bits from the even sense amplifiers and have an odd state that triggers the sensing of the odd bits from the odd sense amplifiers. In a default state (no column errors), multiplexers 125 are then controlled to select for their odd or even inputs depending upon whether Dout is an odd or even word.
Because of the sharing of a single read line 104 across both memory banks, a defect in just the memory bank 1 portion or in just memory bank 0 portion of a given column 135 destroys the usefulness of that even or odd column. Such a defective column is replaced in a sense-amplifier redundancy scheme by a subsequent column for the same odd or even class. To perform this replacement requires a second stage of multiplexers 130.
There is one multiplexer 130 for each word bit. Thus, a first multiplexer 130 selects for Dout[1], a second multiplexer 130 selects for Dout[2], and so on. Because of the two stages of 2:1 multiplexing, each multiplexer 130 except for a last multiplexer 130 for Dout[32] can ultimately select from the bit decisions from two even and odd column pairs. A bit decision from the even and odd column pair for a given word bit may be said to be the unshifted bit decision for that output bit's multiplexer 130. For example, a bit decision from the first bit even and odd columns would be an unshifted bit decision for the multiplexer 130 for Dout[1]. In addition, each multiplexer 130 from the first multiplexer 130 through a next-to-last multiplexer 130 has an S1 input for receiving a hit decision from the subsequent bit's even and odd column pair. This bit decision may be denoted as the shifted bit decision. For example, the first multiplexer 130 can select for the bit decision from the second bit even and odd column pair at its S1 input. But there is no subsequent column for the thirty-second bit's even and odd column. The S1 input for this final bit's multiplexer 130 receives a redundant read line 145 from a redundant column 140. Redundant column 140 includes a redundant sense amplifier 105 for sensing from redundant bit lines 110 in each memory bank.
Note that redundant column 140 can be either an even or odd column depending upon whether memory 100 has a defective even or odd column. In other words, redundant sense amplifiers 105 respond to the sense enable signal regardless of whether the sense enable signal is in the even or odd state. Should there never be any defective columns in memory 100, there would be no need for any multiplexers 130. But in a sense-amplifier shifting scheme, a defective even or odd column is replaced by the immediately subsequent column for its even or odd class. For example, suppose the first bit even column is defective. The function of this initial even column 135 would then be assumed by the second bit even column, which is the subsequent even column to the defective first bit even column.
To enable such a replacement of a given defective even or odd column, each multiplexer 130 can either select for its unshifted (S2) input or a shifted (S1) input. For example, suppose an even column is defective but an odd word is being read from memory 100. In such a case, each multiplexer 130 is controlled to select for its unshifted input. But when an even word is sensed, multiplexers 130 are controlled to select for either their shifted or unshifted input depending upon their bit position with regard to the defective column. For example, suppose the defect is in an ith even column, where i is an integer designating the bit position of the column. Multiplexers 130 prior to this bit position perform no shift. But multiplexers 130 corresponding to the ith bit position and onward are controlled to select for their shifted input. Redundant column 140 would then function as the last (thirty-second in this embodiment) even column. If the ith odd column were defective, an analogous control would occur for multiplexers 130 when an odd word is being read from memory 100. But redundant column 140 would then function as the last odd column. Such SA shifting through multiplexers 125 and 130 demands rather complicated control logic. Moreover, note each even and odd column has its own read line 104, which complicates the resulting routing and layout.
Instead of SA shifting, an I/O shifting redundancy scheme may be implemented. FIG. 2 shows an I/O shifting redundancy scheme for an 8:1 bit line multiplexing (muxing) memory 200. There is no need for a second stage of multiplexers in an I/O shifting redundancy scheme. Instead, a single stage 201 of 2:1 multiplexers 210 can select for the word Dout. In memory 200, the word Dout is again thirty-two bits wide, ranging from bit Dout [1] to bit Dout [32]. Columns 202 are organized as discussed with regard to the even and odd column pairs of memory 100. Thus, each even and odd column pair corresponds to a bit position in Dout in a default (no defective column) state. There is a first pair of even and odd columns corresponding to Dout [1], a second pair corresponding to Dout [2], and so on such that a final column pair (in this embodiment, a thirty-second column pair) corresponds to Dout [32].
Each column 202 comprises the memory cells (not illustrated) and 4 bit lines associated with a corresponding sense amplifier 205, which may be classified as an even or odd sense amplifier depending upon the column type, But unlike memory 100, each read line 206 is shared by a sense amplifier of each type within a memory bank: one odd sense amplifier and one even sense amplifier. To distinguish such a shared read line for a corresponding set of sense amplifiers in a memory bank, read lines 206 will be denoted as load lines. In contrast, the term “read line” will be reserved for applications such as memory 100 in which a read line is not shared by other sense amplifiers within any given memory bank. A load line 206 is shared by the even and odd sense amplifiers in each column pair. Load lines 206 are received by an I/O block 201 including 2:1 multiplexers 210. Like multiplexers 130, each multiplexer 210 can select from an unshifted column pair or a shifted column pair. For example, the multiplexer 210 for Dout[1] can select for the unshifted column pair (the first pair) at its S1 input and for the shifted column pair (the second pair) at its S2 input. But there is no shifted column corresponding to Dout[32]. Thus, the multiplexer 210 for Dout[32] selects for a redundant load line 211 for a redundant column pair 240 as its shifted input.
Because each column pair shares a common load line 206, it will be defective even if just one of its odd or even columns is defective. The I/O shifting thus takes place with regard to sense amplifier pairs (or equivalently, column pairs) and is not sensitive to whether the specific defective column is odd or even. The control logic for multiplexers 210 is thus simplified as compared to a SA shifting scheme. For example, suppose a given column pair is defective. In a default case (no errors), this given column pair corresponds to given one of the output bit positions. This bit position may be designated as Dout [i], where i represents some arbitrary bit. The multiplexers 210 corresponding to Dout [1] through Dout [i−1] select for their unshifted load line whereas the remaining multiplexers 210 select for the shifted load line. The shifting logic is thus rather elementary but I/O shifting requires a redundant column for each word type. For example, if memory 200 were modified to store four types of words (suppose they are named arbitrarily as types A, B, C, and D) as opposed to just storing even and odd words, it would need a redundant A column, a redundant B column, a redundant C column, and a redundant D column. But a SA shifting memory uses a generic column that can substitute for any of the column types. As compared to SA shifting, I/O shifting thus demands more die area. However, another advantage of I/O shifting is that the number of load lines 206 that are routed to multiplexers 210 equals the word width (plus the redundant load line 211). In contrast, the number of read lines for a SA shifting memory will equal a multiple M of the word width (plus the redundant read line 145), where M is an integer representing the number of word types.
There is thus a need in the art for a redundancy scheme that achieves the die savings of sense-amplifier shifting and the control logic simplicity and read-line routing simplicity of I/O shifting.